1. Field of the Invention
The present invention relates to a power amplifier.
2. Description of the Related Art
Recently, blocks constituting a wireless transceiver have been implemented by using a complementary metal oxide semiconductor (CMOS) process technique and tend to be integrated into a single chip. However, among the blocks of the wireless transceiver, only a power amplifier is implemented by using an indium gallium phosphide (InGaP)/gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) process. Compared with the CMOS process, the InGaP/GaAs HBT process incurs high manufacturing costs, is required to have a multi-chip structure, and has difficulty in being coupled to a control circuit block implemented according to the CMOS process to improve linearity. For these reasons, research into a power amplifier based on the CMOS process has been actively ongoing.
Recently, in a case of employing a power amplifier based on the CMOS process in a commonly used wireless communications terminal, a power amplifier having a cascode structure in which two transistors are stacked due to low breakdown voltage characteristics of a CMOS element compared with the case in which the foregoing HBT process is employed, and bias power is supplied to the power amplifier for an amplifying operation.
The bias power is supplied to a common source amplifier in the cascode structure, and in this case, voltage can be applied to a common gate by using a virtual ground formed by connecting both ends of the common gate obtained by the differential structure. In general, an RF open state is equivalently formed by inserting a large resistor at a bias line of the common gate terminal, and here, a signal detected from the common gate node includes a signal of a frequency band corresponding to a baseband generated due to nonlinear characteristics of the common source amplifier, which reduce the linearity of the amplifier.